Research Hypothesis

The leading QC platforms require optimal circuit control and readout while minimising thermal load, external noise, and processing delays. Most quantum hardware is now operated cryogenically well below the minimum CMOS operating temperature of -55°C/218 K for military-grade products, while the control and readout hardware sit physically far away at room temperature (RT) and requires dedicated filtering and thermal attenuation schemes.

Novel control and readout architectures that can be moved close to the quantum hardware will allow for higher gate fidelities (reduced latencies, less noise) and enable scaling (custom integrated circuits of minimized scale per qubit). Also, these new schemes will replace bulky, slow, limited bandwidth RT electronics and the bulky cryogenic RF wiring with enormous heat load that currently prevents the effective scaling up of qubit arrays to the scale required for advanced applications.

The integration of electronics and optical and wireless interconnects near the quantum chip will drive its scalability towards error-corrected QC. The engineering must consider formidable challenges, such as the stringent heating constraints due to limited cryogenic cooling power, wireless and/or optical signal propagation in a cryogenic environment designed to stop radiation to enable deep cryo-cooling, and the disparity of specs for communications, control, and readout among qubit types.

The EPIQC project addresses the technological challenge of scaling up the size of existing quantum simulators and computers, through cross-disciplinary collaboration and co-creation at the interface of QC and ICT.